Skip to main content
 
HOME FOR INVENTORS FOR INDUSTRY FOR ENTREPRENEURS
 

Details

Project TitleEnergy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits
Track Code5479
Short Description

Two energy-efficient pipeline templates for high-throughput asynchronous circuits were developed that greatly minimize handshake circuitry and power consumption by taking advantage of some pre-existing timing assumptions.

Abstract

Two energy-efficient pipeline templates for high-throughput asynchronous circuits were developed that greatly minimize handshake circuitry and power consumption by taking advantage of some pre-existing timing assumptions. By reducing the handshake overhead and energy requirements for asynchronous quasi-delay-insensitive (QDI) circuits, the invention addresses a major constraint of QDI technology (desirable due to its robustness to process variations, lack of dependence on a global clock signal and inherent perfect clock gating), enabling it as a feasible design alternative for future chip design.

Three separate full transistor-level pipelines were implemented and characterized. Compared to a standard QDI pipeline implementation, the Cornell inventions resulted in approximately 40% reduction in energy-delay product and 20% reduction in multiplier latency. Total transistor count was reduced by as much as 54%.

 

Potential Applications:   Next-generation circuits and processors

 

Advantages:   Significantly reduced circuitry and energy overhead for asynchronous circuits

 
TagsChip Engineering (see also Semiconductor), electrical engineering, energy saving, physical science, Semiconductors & Integrated Circuits, signal processing, asynchronous
 
Posted DateJul 23, 2012 6:14 PM

Researcher

Name
Rajit Manohar
Basit Sheikh

Additional Information

Licensing Contact

Martin Teschl

mt439@cornell.edu

(607) 254-4454

Files

File Name Description
Asynchronous Portfolio Manohar.pdf Combined Technology Brief Download