Skip to main content
 
HOME FOR INVENTORS FOR INDUSTRY FOR ENTREPRENEURS
 

Details

Project TitleZero-Delay Wakeup for Power-Gated Circuits
Track Code5109
Short Description

A new “zero-delay” latency hiding wakeup technique for power gated asynchronous circuits was developed that leverages the robustness of asynchronous circuits to delays and supply voltage variations, and can be used with any of the existing power gating schemes.

Abstract

A new “zero-delay” latency hiding wakeup technique for power gated asynchronous circuits was developed at Cornell. The technology leverages the robustness of asynchronous circuits to delays and supply voltage variations, and can be used with any of the existing power gating schemes.

Potential Commercial Applications:

  • Processors, particularly low power, low duty cycle applications, e.g.:
    • Sensor networks
    • USB devices
    • Digital controls
    • Communication systems

Advantages:

  • Reduces power leakage in asynchronous circuits
  • Zero-delay wakeup of pipeline from sleep mode
  • Minimizes voltage fluctuation due to wake-up
  • Power gating scheme agnostic
 
TagsSemiconductors & Integrated Circuits, Chip Engineering (see also Semiconductor), asynchronous, signal processing, physical science
 
Posted DateMay 25, 2012 11:27 AM

Researcher

Name
Rajit Manohar
Carlos Otero
Jonathan Tse

Additional Information

Issued US patent 9,531,194

Ortega, C.; Tse, J.; Manohar, R.; "Static Power Reduction Techniques for Asynchronous Circuits," 2010 IEEE Symposium on Asynchronous Circuits and Systems (ASYNC), May, 2010

Licensing Contact

Martin Teschl

mt439@cornell.edu

(607) 254-4454

Files

File Name Description
Asynchronous Portfolio Manohar.pdf Combined Technology Brief Download
5109 Technology Brief.pdf 5109 Tech Brief Download